Asynchronous Counters

ASYNCHRONOUS COUNTER         

•      It is also known as Ripple or Serial counter.
•    In this counter, all the flip-flops are not under the control of a single clock.
•    The clock pulse is applied to the first flip-flop i.e. the least significant bit stage of the counter.
•    Since the triggers move through the flip-flops like a ripple, it is called a ripple counter.
•    The overall propagation delay time of the counter is the sum of the individual delays of flip-flops.

          4bit Asynchronous UP Counter

Truth table

Logic diagram and Waveforms

Working

   Consider initially that all the flip-flops in the logic 0 state .

 A negative transition(1 to 0) of clock input drives the flip-flop A causes Q_A to change from logic0 to logic1.

Flip-flop B does not change its state since it requires negative transition at its clock input(Q_A).

With the arrival of second clock pulse at flip-flop A, Q_A goes from 1 to 0. This change of state at the flip-flop A creates a negative edge triggering to flip-flop B and thus Q_B goes from 0 to 1.

Before the arrival of the 16^th pulse all the flip-flops are in the logical state.

16^th clock pulse causes Q_A,Q_B,Q_C,Q_D to go to the logic 0 state.

          4bit asynchronous down counter

•    For positive edge triggered flip-flops the counter count down:             e.g start from15 to 14 to 13 to…….
•    The diagram is same as the count up binary counter except that the flip-flop trigger on the positive edge of the clock.
•    If negative edge triggered flip-flops are used then the C input of
• each flip-flop must be connected to the complement output of the previous flip-flop. So, when the true output goes from 0 to 1, the  complement will go from 1 to 0 and complement the next flip flop as required.

Truth table

Logic diagram

Waveforms